Output driver circuits are designed into semiconductor integrated circuits in order to allow integrated circuits to communicate with circuitry external to the integrated circuit via integrated circuit pins. In most cases, a group of output and/or input conductors of an integrated circuit are referred to collectively as a bus. A bus is a group of conductive lines that interconnect several integrated circuits. In most cases, many of the several integrated circuits contain driver circuits that selectively influence the voltage potential of one or more conductors within the bus. For example, a data line or data bus may connect several integrated circuits into a system wherein each integrated circuit is either a microprocessor, an analog device, a memory device, or any other known integrated circuit. Each of the integrated circuits may operate from a different power supply voltage potential. For example, one integrated circuit may operate at five volts, another integrated circuit may operate at 3.3 volts, and yet another integrated circuit may operate at two volts.
Furthermore, in order to increase the number of transistors on an integrated circuit, reduce power dissipation, and increase circuit operational speed, circuit and device geometric dimensions are being gradually reduced through time. The reduced devices are less able to withstand internal integrated circuit electric fields, and are vulnerable to damage and reduced performance when high electric fields are present. In addition, gate oxides of transistors are becoming thinner through time. Thin gate oxides are more susceptible to known and understood reliability failure and breakdown problems than thick gate oxides. Also, channel lengths are being reduced over time. Reduced channel lengths result in known and undesirable hot carrier injection (HCI) effects. In order to overcome the problems listed above, integrated circuits are now being designed for use with lower power supply voltages. For example, 3.3 volts is currently replacing five volts in the industry, and voltages lower than 3.3 volts are expected to be widely used in the near future.
The lower power supply voltages solved many of the problems listed above, but resulted in a new problem that must be solved. The new problem is that it is difficult to interface two integrated circuits or two integrated circuit drivers which operate at different supply voltages.
To further understand the new problem, FIG. 1 is illustrated. FIG. 1 illustrates a first conventional push-pull complementary metal oxide semiconductor (CMOS) output driver within a first integrated circuit 10. The first conventional push-pull CMOS output driver is connected to a second conventional push-pull CMOS output driver located within a second integrated circuit 16. The output stage of a standard push-pull output: driver has a P-channel pull-up transistor illustrated via transistors 12 and 18. N-channel transistors 14 and 20 respectively function as pull-down transistors for each of the output stages of the push-pull output drivers. Integrated circuit 10 is powered by a Vdd power supply labeled "Vdd3" which indicates a 3.3 volt power supply potential. Integrated circuit 16 is powered by a Vdd voltage source labeled "Vdd5" which indicates a 5.0 volt power supply potential. A ground potential is connected to N-channel transistors 14 and 20 as illustrated in FIG. 1.
Separate "drive-hi" signals are used to gate the P-channel transistors 12 and 18 in order to output a logic high signal across the data line. Circuit 10 will drive logic high signal of 3.3 volts and circuit 16 will drive a logic high signal of 5.0 volts. A logic low signal (i.e., ground potential or zero volts) is output along the data line by gating one of the N-channel transistors via a "drive-lo" signal. Usually, "drive-hi" and "drive-lo" are logically designed so that transistors 12 and 14 and transistors 18 and 20 are never "on" simultaneously. Specifically, no more than one transistor among transistors 12, 14, 18, and 20 are in a conductive state at one time. The situation of different integrated circuits having different power supply voltages is becoming very common in modern system designs and modern board-level designs.
The above-described problem occurs when "Vdd5" is significantly greater than "Vdd3" as illustrated in FIG. 1. Assume the alternate driver (integrated circuit 16) is driving a logic high value onto the data line. Therefore transistor 18 is on and transistor 20 is off. Five volts is therefore placed onto the data line. The output stage (i.e., transistors 12 and 14) of integrated circuit 10 is receiving the information from circuit 16 and therefore transistors 12 and 14 are off. In this state, the buffer is said to be tri-stated. When tri-stated, the voltage on the data line will pass to the input circuit as illustrated. The voltage difference between the gate of transistor 12 and the data line is (Vdd5-Vdd3) or roughly 1.7 volts. The drain-to-source voltage magnitude on transistor 12 is also (Vdd5-Vdd3) or roughly 1.7 volts. Since the magnitude of the voltage differential (Vdd5-Vdd3) is greater than the magnitude of the threshold voltage of most MOS transistors (.vertline.Vt.vertline. is usually between 0.5 and 1.5 volts, roughly), transistor 12 will turn on or conduct a significant amount of current.
Because transistor 12 is on, a large current leakage path is formed from the data line to Vdd3 through transistor 12 when circuit 16 sends a logic high value on the data line. Also, a large current may flow from the data line through the n-well to the supply Vdd3 due to the fact that the drain junction diode of transistor 12 is forward biased. Accordingly, high power dissipation, increased integrated circuit heating, and degraded reliability results. Catastrophic circuit failure is now more likely to occur in circuit 10. Therefore, there is a "compatability problem" when interfacing integrated circuits having different voltage supply potentials.
To improve upon the "compatibility problem", several circuits have been implemented in the art. Each of these implementations is discussed below, and each of the circuits discussed below has disadvantages which are also identified.
FIG. 2 illustrates a circuit which is taught by U.S. Pat. No. 4,782,250, issued Nov. 1, 1988, by Adams et al. FIG. 2 illustrates several P-channel transistors 30, 32, 36, and 38 which are formed in a floating n-well (node 40). The n-well is not connected to a particular voltage, but is instead electrically floating. When the voltage at the output enable is zero volts, transistor 28 is off and transistor 36 is on. Therefore, the voltages at "B" and "C" are equalized. The voltage at node "A" is 3.3 volts so transistor 30 is off. Also, transistor 22 is off. Therefore, the driver is in a high impedance state or tri-stated. If an external driver makes the "data output" node equal to five volts, then the transistor 30 turns on raising the voltages at nodes "B" and "C" to five volts. Also, current flows from the data output to the n-well 40 through transistors 30, 32, and 36. The n-well voltage rises to five volts minus a diode threshold voltage drop (roughly 0.7 volts). No current flows from the n-well to the Vdd supply. Transistor 30 is on, but transistor 32 is off (i.e., the circuit is in a tri-state mode). In FIG. 2, there is no high current leakage from the data output to the Vdd terminal as shown/discussed in FIG. 1.
However, the driver illustrated in FIG. 2 has several further disadvantages. One problem is that the driver uses two P-channel pull-up transistors 30 and 32 in series with the Vdd supply. Therefore, each of the transistors 30 and 32 must be twice the size of a single pull-up transistor in order to provide the same current performance as a single pull-up transistor. The increased transistor size results in a 4.times. loss of substrate surface area, which is extremely undesirable since driver transistors are usually large to begin with. Larger transistors also have larger power consumption and larger capacitance than smaller transistors. A second problem is that the circuit of FIG. 2 is susceptible to electrostatic discharge (ESD) damage because transistor 38 has a gate connected directly to the data output node. As gate oxides become thinner, the ESD damage problem becomes enhanced.
A third problem is that the driver of FIG. 2 has excessively high voltages across gate oxides of certain transistors (transistors 30, 32, and 36 in particular). The high voltages across gate oxides occur whenever the n-well acquires high voltages from the data output and retains a high voltage for a long period of time while the Output Enable is at zero volts. Oxide breakdown or oxide leakage may be enhanced by the high voltages. A fourth problem is that transistor 32 is not actively deasserted (i.e., node C is not actively driven to 3.3 volts or 5 volts to turn the transistor off). Furthermore, Node C must be driven from zero volts to a high voltage (3.3 volts to 5.0 volts) through the transistors 30 and 36 which is a slow process. When the data output is driven above 3.3 volts, a high transient current flows from the data output to the supply Vdd through the transistors 30 and 32. Higher power dissipation, increased circuit heating, and excessive loading results due to the transient current.
FIG. 3 illustrates a circuit which is taught by U.S. Pat. No. 4,963,766, issued Oct. 16, 1990, by Lundberg. In FIG. 3, a supply voltage Vdd3 (nominally 3.3 volts) is applied to the output driver circuit. The n-well of the P-channel transistors 50, 51, and 52 is biased to the voltage Vdd5 (nominally 5 volts) which is the supply voltage of an external driver. A gate of transistor 53 is also biased to Vdd5. Because the gate of transistor 53 is biased to Vdd5, the body effect of transistor 53 does not inhibit the drive-hi signal voltage from fully deasserting to 3.3 volts. Therefore, the pull-up transistor 52 turns off. If an external driver then drives the data output node to five volts, transistor 51 turns on raising the voltage at the drive-hi node to roughly five volts. A node 55 maintains a voltage slightly greater than 3.3 volts because of the body effect of transistor 53. Because of the above identified voltage configuration, transistor 52 is off and the p-n junction from the data output to the n-well is not forward biased. Therefore, no high-current leakage results between the data output and Vdd3 as discussed in reference to FIG. 2.
However, the driver of FIG. 3 has several disadvantages. The first problem is that the driver requires a dedicated pin on the integrated circuit to provide the voltage Vdd5 in addition to the voltage Vdd3. A second problem is that the circuit in FIG. 3 allows excessively high voltages across the gate oxides of various transistors during operation. For example, when Drive-Hi is equal to zero volts, the transistor 52 has a large potential difference across the gate oxide of transistor 52. Oxide reliability is degraded, and the likelihood of oxide breakdown is increased. A third problem is that the driver has a low-current leakage path from the data output to the supply Vdd3 when the driver is in the high impedance state and an external driver drives the output to five volts. This low-current leakage path is through the transistors 50, 51, and 53. Power consumption and input-high current loading (I.sub.ih loading) are both increased, which is disadvantageous.
A third circuit that partially solves the compatibility problem has been documented by Dobberpuhl, et al., in the IEEE Journal of Solid State Circuits, Vol. 27, No. 11, November 1992, pp. 1555-1567 and is shown in FIG. 4. In this circuit, the bulk node of the p-channel transistors, 64, 65, 66, 67, 68, 69, and 60, is a floating n-well. The n-well is preferably formed as at least one diffusion region/well within a semiconductor substrate. There is only one pull-up transistor labeled transistor 66. Usually, the n-well voltage is 3.3 volts. After the drive-high signal is deasserted and the circuit is put into the high impedance state, the voltage on node 3 is 0 volts, and the voltage on node 5 is 3.3 volts. The inverter in FIG. 4 drives node 4 to 3.3 volts. Due to the fact that the transistor 65 is off, the voltage on node 6 rises only to around (Vdd3-.vertline.Vth, body.vertline.). In other words, .vertline.Vth, body.vertline. is greater than .vertline.Vth.vertline. and .vertline.Vtp.vertline.=.vertline.Vtn.vertline. and therefore transistor 66 is not fully off. Therefore, the driver is not truly in the high impedance state. This is disadvantageous. If an external alternate driver subsequently drives node 8 to a voltage greater than 3.3 volts (i.e., drives the output node to 5 volts), then transistor 69 turns on, raising the voltage of the n-well to 5 volts. Also, transistor 64 turns on, raising the voltage on node 6 to 5 volts. Accordingly, the voltage on nodes 5 and 7 will also rise to 5 volts. Because of this voltage configuration, transistor 66 is off, and the p-n diode from the output to the n-well is not forward biased. Therefore, there is no high-current leakage as discussed above for other output buffer circuits. The reduction in leakage current is advantageous.
However, the driver taught by Dobberpuhl et al. has several disadvantages. One problem is that the circuit is susceptible to ESD damage because transistors 65 and 67 have their respective gate nodes connected to the output node 8. Although the gate nodes are somewhat protected by resistors R1 and R2, an ESD event at the output node could rupture the gate oxide of the transistors 65 and/or 67, especially if the transistors are fabricated using a thin-oxide process (i.e., roughly 70-150 Angstroms). Also, transistor 61 is off and transistor 66 is on the boundary between its off state and its conducting state, which is disadvantageous.
A second problem is that the driver of FIG. 4 can suffer from high crossover current in some applications when driving the output to zero volts. To illustrate this crossover current, the voltage on node 5 is initially 3.3 volts or higher. As has been discussed above, when the inverter drives the voltage on node 4 to 3.3 volts to turn off the pull-up transistor, transistor 65 is off, and the voltage on node 6 rises in voltage to (Vdd3-.vertline.Vth, body.vertline. of transistor 63) because of the body effect of transistor 63. Due to the fact that the threshold voltage of 63 is proportional to the square root of the source to bulk voltage and the source node of 63 is connected to the gate of the pull-up transistor, the threshold voltage increases as the voltage on the gate of the pull-up transistor increases, limiting the voltage on node 6. Electrical coupling from the overlap capacitance of the pull-up transistor 66 further decreases the voltage on node 6. The pull-up transistor 66 is not fully off. The voltage on node 2 rises to 3.3 volts, turning transistor 61 on. Thus, for a time, both the pull-up transistor 66 and pull-down transistors 61 and 62 conduct a significant amount of crossover current from the supply voltage to ground. The crossover current increases chip heating, increases power dissipation, increases the output transition time, and decreases noise immunity.
A third problem is that the driver of FIG. 4 suffers from excessively high voltages across the gate oxides of certain transistors in the circuit. If the driver is in the high impedance state, and an external alternate driver drives the output node to five volts, the n-well voltage rises to five volts, as described above. The n-well voltage can be even higher under other circumstances (e.g., transmission line effects, noise, etc.). If the next operation of the circuit causes the driver to drive the output node to 3.3 volts, the voltage on node 3 (drive-high) will rise to 3.3 volts. The inverter drives the voltage on node 4 to 0 volts. The voltage on node 6 discharges to zero volts through pass transistor 63. The n-well can retain its voltage of 5 volts, or more, for a relatively long time, resulting in an excessively high transient voltage across the gate oxide of transistor 66 since the transistors 64 and 69 are both in the n-well discharge path. This voltage situation usually degrades the oxide reliability of 66 and can lead to oxide breakdown. If instead of driving the output node to 3.3 volts, the driver drives the output node to zero volts, the voltage on node 2 rises to 3.3 volts. As node 5 discharges to zero volts, the discharging of node 5 may result in an excessively high transient voltage across the gate oxide of transistors 65 and 67 and can degrade the reliability of these transistors.
Therefore, a need exists for an output buffer circuit which overcomes the disadvantages discussed above.